Design of High-Speed GNRFET-Based Analog to Digital Converter

Abstract

This work presents the design and simulation of two-, three-, and four-bit analog-to-digital converters (ADCs) utilizing Graphene Nano Ribbon Field Effect Transistors (GNRFETs). The GNRFET devices employed in this design had a channel length of 16 nm and were operated at a supply voltage of 0.7 V. Advanced Design System (ADS) was used as the simulation platform. To achieve a compact and efficient design, a current mirror topology was implemented for biasing. Each ADC configuration was evaluated in terms of power consumption. Within the 0.7 V supply voltage, the designs exhibited a full-range linear input characteristic. These results indicate that this ADC design is particularly well-suited for applications in high-speed nano-electromechanical systems (NEMS), memory cells, and advanced computing architectures. The average percentage reduction in delay is 12% for standard transistor logic (STI) and 32% for the ADC design, respectively. Additionally, power-optimized ternary logic circuits tend to operate faster.