An Ultra Lightweight Hardware Efficient Cryptography Algorithm For Wireless Sensor Networks (WSNs)

Abstract

A Wireless Sensor Network (WSN) is made up of numerous low-cost and low power sensor nodes. There is a great demand for energy-efficient operations since nodes in a WSN are typically very energy-constrained and must operate for extended periods of time using finite  on-board energy reserves. One method of conserving the node’s energy is through hardware circuitry. This paper presents an area-efficient implementation of SLIM, an ultra-lightweight cryptographic algorithm. The proposed SLIM method utilizes an iterative architecture that enables the reuse of hardware components for each round of computation. To further minimize area utilization, FPGA Block RAMs (BRAMs) are employed. The design targets the Spartan 3 FPGA, featuring block sizes of 32 bits and a key size of 80 bits. Simulation results indicate that this approach achieves effective area utilization, which can significantly lower power consumption compared to the original architecture, making it suitable for energy-constrained devices.